Ecosyste.ms: Timeline

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timothytrippel

timothytrippel pushed 1 commit to master lowRISC/opentitan
  • [imm_rom_ext] Add a new ROM_EXT target linking nop IM_EXT * Add a nop.o IM_EXT file, which is built by `./riscv32-... 2cf0b0e

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timothytrippel created a review on a pull request on lowRISC/opentitan

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timothytrippel created a review comment on a pull request on lowRISC/opentitan
We should probably make this parameter optional in the orchestrator.py script too: https://cs.opensource.google/opentitan/opentitan/+/earlgrey_1.0.0:sw/host/provisioning/orchestrator/src/ot_dut.py;...

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timothytrippel created a review on a pull request on lowRISC/opentitan

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timothytrippel pushed 1 commit to update-prov-fw timothytrippel/opentitan
  • [manuf] refactor CP init to read out wafer data and device ID When CP init runs, flash info page 0 will already be p... c470bde

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timothytrippel created a review comment on a pull request on lowRISC/opentitan
@benjbender if you could enlighten me on the encoding of the lot name, I could address the "TODO" below on line 114, and validate the second word of the CP device ID contains the correct "year", "w...

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timothytrippel created a review on a pull request on lowRISC/opentitan

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timothytrippel pushed 1 commit to update-prov-fw timothytrippel/opentitan
  • [manuf] refactor CP init to read out wafer data and device ID When CP init runs, flash info page 0 will already be p... 9432f15

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timothytrippel pushed 1 commit to update-prov-fw timothytrippel/opentitan
  • [manuf] refactor CP init to read out wafer data and device ID When CP init runs, flash info page 0 will already be p... b55ebe3

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timothytrippel created a review comment on a pull request on lowRISC/opentitan
Ah looks like those just got moved around as a part of `bazel run //quality:buildifier_fix` running. Not sure why CI didn't catch that before. They were already in place though.

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timothytrippel created a review on a pull request on lowRISC/opentitan

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timothytrippel created a review comment on a pull request on lowRISC/opentitan
to match #25387

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timothytrippel created a review on a pull request on lowRISC/opentitan

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timothytrippel created a review comment on a pull request on lowRISC/opentitan
@cfrantz @moidx We should update this to log (via JSON) the CP portion of the device ID so the orchestrator script can pick this up and update it with the FT portion (https://docs.google.com/docume...

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timothytrippel created a review comment on a pull request on lowRISC/opentitan
@benjbender please confirm these offsets

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timothytrippel created a review on a pull request on lowRISC/opentitan

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timothytrippel opened a pull request on lowRISC/opentitan
[manuf] refactor CP init to read out wafer data and device ID
When CP init runs, flash info page 0 will already be provisioned with wafer data from prior CP stages. This updates the CP init and subsequent FT provisioning stages to assume that is the case and ...
timothytrippel pushed 25 commits to update-prov-fw timothytrippel/opentitan
  • [ownership] Compute correct flash INFO page addresses Signed-off-by: Chris Frantz <[email protected]> (cherry picke... f793a4e
  • [ownership] Test an INFO page configuration Add an INFO page to the various `with-flash` configurations in the owner... e6c2bfe
  • [ci] Remove ROM e2e test cases from earlgrey_1.0.0 Note: Do not merge this change directly into the `master` or any ... 2e659b1
  • [signing] Initial sign of ROM_EXT and provisioning binaries 1. Add the real `sival` SKU provisioning configuration a... b0c4cdd
  • [rules] Specify fusesoc cache dir to be in the bazel tree Make the fusesoc cache dir be in the bazel tree, so fuseso... 67acdaa
  • [SiVal, testplans] Fixes SiVal stage on testplans Signed-off-by: Douglas Reis <[email protected]> (cherry picked fr... c5b1d50
  • [SiVal, testplans] Add missing references to earlgrey chip Signed-off-by: Douglas Reis <[email protected]> (cherry ... 12777dc
  • [SiVal] Remove unnexisting bazel target Signed-off-by: Douglas Reis <[email protected]> (cherry picked from commit ... 28a5db0
  • [SiVal] Update testsuites Signed-off-by: Douglas Reis <[email protected]> (cherry picked from commit a61b9e31cbdb99... 17928c0
  • [ci] Move Verilated Earl Grey tests to GitHub Actions Signed-off-by: James Wainwright <[email protected]>... 9406ed6
  • Port sleep_pin_wake to SiVal This is a manual cherry-pick of https://github.com/lowRISC/opentitan/pull/23472 Signed... 4f91994
  • [pwrmgr] Add suffix _test for consistency Signed-off-by: Douglas Reis <[email protected]> (cherry picked from commi... c51e051
  • [pwrmgr] Skip OTP test when running with ROM_EXT The ROM_EXT locks up the OTP register in the ePMP, any attempt to w... 68d8ff2
  • [Sival, pwrmgr] Adds chip_sw_power_sleep_load test and link in testplan Signed-off-by: Douglas Reis <doreis@lowrisc.... bfbd847
  • [pwrmgr] Refactor constants names as the coding style guide Signed-off-by: Douglas Reis <[email protected]> (cherry... 53c49b0
  • [pwrmgr] Refactor comments for consistency Signed-off-by: Douglas Reis <[email protected]> (cherry picked from comm... a7c7bc1
  • [sival, i2c] Add silicon exec_env to tests Signed-off-by: Douglas Reis <[email protected]> (cherry picked from comm... c8a6541
  • [sival] Assign `gpio_pinmux_test` to two points This test checks various muxing configurations, plus one attribute (... e269618
  • [rom_ext] Clean up ROM_EXT prints 1. Change the startup banner to just "ROM_EXT:<version>". 2. Prefix all ROM_EXT me... 2df15e7
  • [sival] Improve reliability of UART baud rate test Signed-off-by: James Wainwright <[email protected]> (c... 62a7c0c
  • and 5 more ...

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timothytrippel created a review on a pull request on lowRISC/opentitan

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timothytrippel closed an issue on lowRISC/opentitan
[manuf] provision owner configuration block during personalization
### Description When the chip is personalized, an owner configuration block may be provisioned so that a post-provisioning ownership transfer process does not need to be run on each device. Integr...
timothytrippel pushed 53 commits to master timothytrippel/opentitan
  • [sival] Add SiVal environments to flash_ctrl_info_access The ROM_EXT version is currently broken but we expect it to... dfccd12
  • [sival] Add CW310 exec_env to rv_dm tests These work on both the CW310 and CW340. Signed-off-by: James Wainwright <... 3c448b4
  • [topgen] Add function to render AC range checks Signed-off-by: Robert Schilling <[email protected]> 974c0e1
  • [hw,ac_range_check,rtl] Initial register description and top-level Signed-off-by: Robert Schilling <rschilling@rivos... 02f73e6
  • [hw,ac_ranges,doc] Port over the RFC documentation Signed-off-by: Robert Schilling <[email protected]> e51d3f5
  • [hmac,doc] Update for arbitrary key length - The HMAC supports arbitrary key lengths. Add precision on how to use ... 5d1b525
  • [pentest] Add OTBN FI tests This PR pulls over the following tests: - otbn.fi.char.jal - otbn.fi.char_dmem_access - ... 2c3f55b
  • [pentest] Add RSA512 decryption SCA test This commit adds the otbn.sca.rsa512_decrypt penetration test. The user nee... 9b0647a
  • [hw,pinmux,lint] Correctly gate all unused signals Signed-off-by: Robert Schilling <[email protected]> c6f01ff
  • [hw,rv_dm,lint] Remove unused signals and tie-offs Signed-off-by: Robert Schilling <[email protected]> f1f6ce2
  • [hw,kemgr(_dpe),rtl] Parametrize rom_digets for input checks Signed-off-by: Robert Schilling <[email protected]> 8b114c1
  • [hw,dma,lint] Update SHA message size for new prim Signed-off-by: Robert Schilling <[email protected]> 4fae52f
  • [hw,pinmux] Gate countermeasures only used for HW strampling Signed-off-by: Robert Schilling <[email protected]> 58c09d7
  • [darjeeling] Add core and linter files for Darjeeling Signed-off-by: Robert Schilling <[email protected]> 649b711
  • [darjeeling] Add top-dependend RTL files Add jtag_id_pkg.sv, padring.sv, scan_role_pkg, ibex_pmp_reset_pkg.sv padrin... 8f279ef
  • [hw,pinmux,rtl] Move signal definition outside of param block The mi/dio signals are used in both cases, hardware st... a321e4e
  • [hw,prim_ram_1r1w,lint] rst_a_ni is only used in assertions in some configs Signed-off-by: Robert Schilling <rschill... b04e6c6
  • [darjeeling,templates] Update Darjeeling templates and top_pkg to include CTN Signed-off-by: Robert Schilling <rschi... 25eb11d
  • [darjeeling,ast,rtl] Remove devmode_i and fix core files Signed-off-by: Robert Schilling <[email protected]> 2bc4f81
  • [darjeeling,sensor_ctrl,rtl] Remove devmode_i Signed-off-by: Robert Schilling <[email protected]> 0171b58
  • and 33 more ...

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timothytrippel pushed 20 commits to earlgrey_1.0.0 timothytrippel/opentitan
  • [rules] Specify fusesoc cache dir to be in the bazel tree Make the fusesoc cache dir be in the bazel tree, so fuseso... 67acdaa
  • [SiVal, testplans] Fixes SiVal stage on testplans Signed-off-by: Douglas Reis <[email protected]> (cherry picked fr... c5b1d50
  • [SiVal, testplans] Add missing references to earlgrey chip Signed-off-by: Douglas Reis <[email protected]> (cherry ... 12777dc
  • [SiVal] Remove unnexisting bazel target Signed-off-by: Douglas Reis <[email protected]> (cherry picked from commit ... 28a5db0
  • [SiVal] Update testsuites Signed-off-by: Douglas Reis <[email protected]> (cherry picked from commit a61b9e31cbdb99... 17928c0
  • [ci] Move Verilated Earl Grey tests to GitHub Actions Signed-off-by: James Wainwright <[email protected]>... 9406ed6
  • Port sleep_pin_wake to SiVal This is a manual cherry-pick of https://github.com/lowRISC/opentitan/pull/23472 Signed... 4f91994
  • [pwrmgr] Add suffix _test for consistency Signed-off-by: Douglas Reis <[email protected]> (cherry picked from commi... c51e051
  • [pwrmgr] Skip OTP test when running with ROM_EXT The ROM_EXT locks up the OTP register in the ePMP, any attempt to w... 68d8ff2
  • [Sival, pwrmgr] Adds chip_sw_power_sleep_load test and link in testplan Signed-off-by: Douglas Reis <doreis@lowrisc.... bfbd847
  • [pwrmgr] Refactor constants names as the coding style guide Signed-off-by: Douglas Reis <[email protected]> (cherry... 53c49b0
  • [pwrmgr] Refactor comments for consistency Signed-off-by: Douglas Reis <[email protected]> (cherry picked from comm... a7c7bc1
  • [sival, i2c] Add silicon exec_env to tests Signed-off-by: Douglas Reis <[email protected]> (cherry picked from comm... c8a6541
  • [sival] Assign `gpio_pinmux_test` to two points This test checks various muxing configurations, plus one attribute (... e269618
  • [rom_ext] Clean up ROM_EXT prints 1. Change the startup banner to just "ROM_EXT:<version>". 2. Prefix all ROM_EXT me... 2df15e7
  • [sival] Improve reliability of UART baud rate test Signed-off-by: James Wainwright <[email protected]> (c... 62a7c0c
  • [sival,hmac] Update HMAC testplan - Remove KMAC test target - Specify testing all HMAC-SHA2 modes - Add test targets... 2034a21
  • [sival,kmac] Update KMAC testplan - Add cSHAKE KAT tests - Remove mentions of XOF from KMAC testpoint. These are cov... e683afd
  • [sival,kmac] Add SHA3 NIST CAVP KAT tests Signed-off-by: Miles Dai <[email protected]> (cherry picked from comm... 2b68995
  • [provisioning] Recognize the old ROM_EXT output The ROM_EXT used to print "Starting ROM_EXT 0.1", but we cleaned up ... 040c235

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timothytrippel deleted a branch cfrantz/opentitan

rom_ext-prints

timothytrippel created a review on a pull request on lowRISC/opentitan

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timothytrippel deleted a branch cfrantz/opentitan

a1_signing

timothytrippel pushed 1 commit to earlgrey_1.0.0 lowRISC/opentitan
  • [signing] Initial sign of ROM_EXT and provisioning binaries 1. Add the real `sival` SKU provisioning configuration a... b0c4cdd

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timothytrippel created a branch on timothytrippel/opentitan

update-prov-fw - OpenTitan: Open source silicon root of trust

timothytrippel deleted a branch lowRISC/opentitan

backport-25308-to-master

timothytrippel pushed 1 commit to master lowRISC/opentitan
  • [openocd] fix openocd build on new versions of GCC We configure GCC to treat all warnings as errors and newer versio... 020beeb

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