Ecosyste.ms: Timeline
Browse the timeline of events for every public repo on GitHub. Data updated hourly from GH Archive.
timothytrippel closed a pull request on lowRISC/opentitan
[sival] Remove unused OTP targets from sival SKU.
The provisioning firmware contains hardcoded settings for the HWCFG1 partition, and uses data generated at manufacturing time to calculate the DEVICE_ID. As a result, most of the otp image targets ...
timothytrippel created a review comment on a pull request on lowRISC/opentitan
This does not need to a be a hardened check. It can just be an ordinary `TRY_CHECK(x == y)` https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/lib/testing/test_framework/check.h;l=...
timothytrippel closed a pull request on lowRISC/opentitan
Cherry-pick to earlgrey_1.0.0: [ot_certs] Various fixes
This is an automatic cherry-pick of #25124 to branch `earlgrey_1.0.0`.
timothytrippel created a review comment on a pull request on lowRISC/opentitan
If this merges before #25178, then I will update #25178 to change the 0x0 to `CONST.MANUF_STATE.PERSONALIZED`.
timothytrippel opened a pull request on lowRISC/opentitan
[cherry-pick] manual cherry-pick of #24948, #25087, and #25106 to `earlgrey_1.0.0`
This cherry-picks several commits to `earlgrey_1.0.0` that prevent the personalization firmware from executing again once a device has been successfully personalized.
timothytrippel created a branch on timothytrippel/opentitan
cp-no-perso-rerun - OpenTitan: Open source silicon root of trust
timothytrippel pushed 22 commits to earlgrey_1.0.0 timothytrippel/opentitan
- [bazel] Ensure output files of outquery are unique Resolves OpenTitan/Issue#23990. Some scripts rely on the fact tha... dfc342a
- [sw,dv] Add basic `status_t` (%r) logging in DV Adds a simple substitution rule to the current C->SV logging backdoo... c737009
- [sival,i2c] Fix and re-enable I2C target test The I2C target test was failing because the ujson I2cTestConfig comman... 8024ff6
- [SiVal, spi_host] Update execution environment of macronix test Signed-off-by: Douglas Reis <[email protected]> (ch... 8cc947b
- [sival] Fix Bazel target for UART parity test This test was renamed but its reference in the testplan was not. Sign... 849c9cb
- [sival] Include cryptolib tests in earlgrey sival testplan These tests must pass for silicon validation, so we shoul... 1601fcd
- [sival] Fix NA stage for crypto tests The dvsim test plan checker does not like the NA spelling. Signed-off-by: Jam... bd13ee5
- [build] Introduce OTP emulation images. This change is in preparation for managing the SiVal silicon configuration u... 1161579
- [opentitanlib] add function to print LC state in readable form This adds a member function to the DifLcCtrlState enu... 92b000f
- [opentitanlib] silence openocd log messages This silences unecessary openocd console messages and adds a CLI arg to ... b77f530
- [manuf,cp] fix bug in parsing test token args This fixes a bug in how the test token args were parsed. Previously, t... 5420d89
- [manuf] fix flash info 0 data print in CP and FT This fixes the print format strings for the device ID, AST config, ... 1f4d9de
- [manuf,bazel] remove data deps from host CP and FT bins Previously, the host CP and FT test harnesses had data depen... 68bc33f
- [provisioning] add device_id, sku_config, and ca_config modules This adds several modules to: 1. build and validate ... b59b033
- [provisioning] add initial orchestrator script This adds an initial version of the orchestrator script for benchtop ... 00b47ae
- [SiVal] Revert commit f2d77268da5bb6f1a00e5bef3e506ac5d39da740 Signed-off-by: Douglas Reis <[email protected]> (che... b4dba3c
- [SiVal] Add si_stage to rom_e2e testplan Signed-off-by: Douglas Reis <[email protected]> (cherry picked from commit... 8b17c50
- [SiVal] Add si_stage to tlul testplan Signed-off-by: Douglas Reis <[email protected]> (cherry picked from commit 17... ef957c9
- [SiVal] Update si_stage of ibex_lockstep_glitch test Signed-off-by: Douglas Reis <[email protected]> (cherry picked... 1b9f37a
- [ownership] Add datatypes for hybrid keys Signed-off-by: Chris Frantz <[email protected]> f562c7e
- and 2 more ...
timothytrippel opened a pull request on lowRISC/opentitan
[cherry-pick] manually cherry-pick of #24980 and #25136 onto `earlgrey_1.0.0` branch
This cherry pick includes a bug fix to the ROM_EXT that ensures the DICE CDI_1 private is left in OTBN DMEM when the owner firmware is booted. Additionally, this adds a ROM_EXT E2E test to ensure t...
timothytrippel created a branch on timothytrippel/opentitan
fix-rom-ext-cert-update - OpenTitan: Open source silicon root of trust
timothytrippel pushed 8 commits to master timothytrippel/opentitan
- [cryptotest] Add AES KAT vector to documentation Signed-off-by: Miles Dai <[email protected]> aac7744
- [cryptotest] Remove dependence on vendored AES KAT test vectors Signed-off-by: Miles Dai <[email protected]> 9dc6779
- [cryptotest] Remove redundant SHA3 testvectors These hardcoded test vector files contain vectors from the NIST CAVP ... 2e4474a
- [cryptotest] Add CSHAKE NIST example values to KAT tests Signed-off-by: Miles Dai <[email protected]> 299a18c
- [cryptotest] Add missing CSHAKE sample test vectors The original hardcoded hjson file in the repo was missing test c... c119b8c
- [cryptotest] Remove redundant SHAKE testvectors shake128_hardcoded.hjson - Test cases 1-3 are already included in @n... 6c87274
- [ci] Port software build job from Azure to GitHub Signed-off-by: James Wainwright <[email protected]> 0b0aeb3
- [ci] Move `sw_test` to GitHub Actions Merged into `sw_build` since this part should be fairly quick. Signed-off-by:... e8f7699
timothytrippel created a review comment on a pull request on lowRISC/opentitan
basically the final cleanup is renaming the `sival` [rom_ext](https://cs.opensource.google/opentitan/opentitan/+/earlgrey_1.0.0:sw/device/silicon_creator/rom_ext/sival/) `emulation` and binding thi...
timothytrippel pushed 2 commits to cleanup-orchestrator timothytrippel/opentitan
timothytrippel pushed 46 commits to provisioning-bug-fixes timothytrippel/opentitan
- [ot_certs] Make parse test reproducible on failure Always print the test data so that if other operations fail (prod... c008362
- [ot_certs] Make sure to generate valid random times OpenSSL can be quite picky with dates so make sure that when we ... f5df1fc
- [ot_certs] Parse Authority and Subjecy Key Identifier manually OpenSSL has an undocumented quirk: if the basic key u... a58a116
- [uart,dv] Mitigate dly from CSR reads in intr test Two tweaks to avoid failures of `uart_intr_vseq`. When testing R... 8a4f597
- [pwm,rtl] Make calculation of some _d signals in pwm_chan.sv clearer This is equivalent but should be rather easier ... 73fa985
- [pwm,dv] Avoid running as UVM_HIGH by default I think the initial commit of this code included a run mode as default... 33a0e52
- [pwm,dv] Set a sensible timeout for slowest clocks The default timeout is 0.2 seconds and at a 5MHz clock, we're not... c41f21a
- [pwm,dv] Use out-of-block declarations in pwm_rand_output_vseq Signed-off-by: Rupert Swarbrick <[email protected]> 094a0ef
- [pwm,dv] Use out-of-block declarations in pwm_smoke_vseq Signed-off-by: Rupert Swarbrick <[email protected]> 5d837ae
- [pwm,dv] Use out-of-block definitions in pwm_stress_all_vseq Signed-off-by: Rupert Swarbrick <[email protected]> f4addf2
- [tlgen] Reduce minimum spacing to 0x100 Darjelling uses 0x100 spaced devices on the mbx xbar Signed-off-by: Robert ... 8f02a25
- [darjeeling,templates] Fix FPGA config for chip-level template Signed-off-by: Robert Schilling <rschilling@rivosinc.... c823527
- [top_darjeeling,ast] Add AST for Darjeeling Signed-off-by: Robert Schilling <[email protected]> 788c5cf
- [top_darjeeling,sensor_ctrl] Add sensor_ctrl for Darjeeling Signed-off-by: Robert Schilling <[email protected]> 1fb988b
- [pinmux] Feed through mio_i/dio_i signals Signed-off-by: Robert Schilling <[email protected]> 3d3dcfd
- [topgen] Use top-level overwritten parameter when doing inter-signal checks Signed-off-by: Robert Schilling <rschill... 6120174
- [topgen] Enable wait for reset only for Darjeeling Signed-off-by: Robert Schilling <[email protected]> b4b8816
- [topgen] Enable strap sampling / usb wakeup for Earlgrey/Englishbreakfast Signed-off-by: Robert Schilling <rschillin... 28c6d7d
- [SiVal] Revert commit f2d77268da5bb6f1a00e5bef3e506ac5d39da740 Signed-off-by: Douglas Reis <[email protected]> 8628570
- [SiVal] Add si_stage to rom_e2e testplan Signed-off-by: Douglas Reis <[email protected]> f0e2874
- and 26 more ...
timothytrippel pushed 40 commits to master timothytrippel/opentitan
- [ot_certs] Make parse test reproducible on failure Always print the test data so that if other operations fail (prod... c008362
- [ot_certs] Make sure to generate valid random times OpenSSL can be quite picky with dates so make sure that when we ... f5df1fc
- [ot_certs] Parse Authority and Subjecy Key Identifier manually OpenSSL has an undocumented quirk: if the basic key u... a58a116
- [uart,dv] Mitigate dly from CSR reads in intr test Two tweaks to avoid failures of `uart_intr_vseq`. When testing R... 8a4f597
- [pwm,rtl] Make calculation of some _d signals in pwm_chan.sv clearer This is equivalent but should be rather easier ... 73fa985
- [pwm,dv] Avoid running as UVM_HIGH by default I think the initial commit of this code included a run mode as default... 33a0e52
- [pwm,dv] Set a sensible timeout for slowest clocks The default timeout is 0.2 seconds and at a 5MHz clock, we're not... c41f21a
- [pwm,dv] Use out-of-block declarations in pwm_rand_output_vseq Signed-off-by: Rupert Swarbrick <[email protected]> 094a0ef
- [pwm,dv] Use out-of-block declarations in pwm_smoke_vseq Signed-off-by: Rupert Swarbrick <[email protected]> 5d837ae
- [pwm,dv] Use out-of-block definitions in pwm_stress_all_vseq Signed-off-by: Rupert Swarbrick <[email protected]> f4addf2
- [tlgen] Reduce minimum spacing to 0x100 Darjelling uses 0x100 spaced devices on the mbx xbar Signed-off-by: Robert ... 8f02a25
- [darjeeling,templates] Fix FPGA config for chip-level template Signed-off-by: Robert Schilling <rschilling@rivosinc.... c823527
- [top_darjeeling,ast] Add AST for Darjeeling Signed-off-by: Robert Schilling <[email protected]> 788c5cf
- [top_darjeeling,sensor_ctrl] Add sensor_ctrl for Darjeeling Signed-off-by: Robert Schilling <[email protected]> 1fb988b
- [pinmux] Feed through mio_i/dio_i signals Signed-off-by: Robert Schilling <[email protected]> 3d3dcfd
- [topgen] Use top-level overwritten parameter when doing inter-signal checks Signed-off-by: Robert Schilling <rschill... 6120174
- [topgen] Enable wait for reset only for Darjeeling Signed-off-by: Robert Schilling <[email protected]> b4b8816
- [topgen] Enable strap sampling / usb wakeup for Earlgrey/Englishbreakfast Signed-off-by: Robert Schilling <rschillin... 28c6d7d
- [SiVal] Revert commit f2d77268da5bb6f1a00e5bef3e506ac5d39da740 Signed-off-by: Douglas Reis <[email protected]> 8628570
- [SiVal] Add si_stage to rom_e2e testplan Signed-off-by: Douglas Reis <[email protected]> f0e2874
- and 20 more ...
timothytrippel opened a pull request on lowRISC/opentitan
[provisioning] remove crc32 from device ID and testonly flags from CP/FT harnesses
This contains two commits that address review feedback in #25151 and #25152. Specifically, this: 1. removes the CRC32 field from the device ID and marks it as reserved, and 2. removes `testonly...
timothytrippel created a branch on timothytrippel/opentitan
cleanup-orchestrator - OpenTitan: Open source silicon root of trust
timothytrippel created a review comment on a pull request on lowRISC/opentitan
It is because all the FPGA exec_envs are marked as "testonly" so it forces this downstream.
timothytrippel created a comment on a pull request on lowRISC/opentitan
Now we have the emulation OTP config, we can probably cleanup the extra images in sival: https://cs.opensource.google/opentitan/opentitan/+/earlgrey_1.0.0:hw/ip/otp_ctrl/data/earlgrey_skus/sival/BU...